1. Field of the Invention
The present invention relates to a MOS resistance controlling device for controlling the resistance between the source and drain of a MOS transistor and a MOS attenuator having the MOS resistance controlling device.
2. Description of the Related Art
A MOS transistor is widely available as a resistance element for various electronic circuits. In this case, the linear region of the MOS transistor is utilized. In the linear region of the MOS transistor, the resistance “Rmos” between the drain and source of the MOS transistor can be approximately represented by the equation of Rmos≈1/{β·(Vgs−Vth)}. Herein, β=(μn·Cox)·(W/L) (μn: electron mobility, Cox: gate oxide capacitance per unit area, L: gate length of MOS transistor, W: gate width of MOS transistor, Vgs: voltage between gate and source of MOS transistor, Vth: threshold voltage). Therefore, the resistance “Rmos” can be varied by changing the gate voltage Vgs.
A MOS resistance controlling circuit is exemplified in Reference 1, and uses a feedback circuit with an operational amplifier. Schematically, the gate voltage to realize the intended MOS resistance is obtained through the feedback of the voltage between the source and drain of the MOS transistor to the operational amplifier. In this case, the gate voltage is applied to the gate of another MOS transistor so that another MOS transistor is controlled so as to have the intended MOS resistance.
A variable attenuator is disclosed in Reference 2 as an application circuit using the MOS resistance. Schematically, the MOS resistances are employed as a ground resistance and a passing resistance, respectively and the gate voltage of the MOS transistor to ground is varied so as to realize the variable attenuator. Since the characteristic impedance of the attenuator is shifted from a predetermined value (rendered non-matching state) if only the ground resistance is changed, a prescribed voltage is applied to the gate of the passing MOS transistor so that the characteristic impedance of the attenuator is set to the predetermined value. In order to obtain the predetermined voltage, a dummy circuit (replica) with a circuit structure similar to the one of the variable attenuator and a feedback circuit with an operational amplifier are provided.
The voltage generated according to Reference 1 can be supplied to the gate of the ground MOS transistor. In this case, even though the characteristics (e.g., threshold voltages) of the ground MOS transistor and the MOS transistor to supply the gate voltage are shifted similarly, the attenuation can be controlled precisely by the combination of the MOS transistors. However, if the operational amplifier in the controlling circuit of the MOS resistance has a DC offset, the variable attenuator is affected by the DC offset of the operational amplifier. References 1 and 2 do not teach the means for mitigating the above-described problem.                [Reference 1] JP-A 10-200334 (KOKAI)        [Reference 2] Hakan Dogan, Robert G. Meyer and Ali M. Niknejad BWRC, UC Berkeley, “A DC-10 GHZ Linear-in-dB Attenuator in 0.13 μm CMOS Technology”, IEEE 2004 CUSTOM INTEGCONSTANT CIRCUITS CONFERENCE pp 609 to 612        